1. Technical Field
The present disclosure relates to an integrated circuit semiconductor device and a method of fabricating the same. More particularly, the present invention relates to an integrated circuit semiconductor device with an overlay key and an alignment key and a method of fabricating the same.
2. Discussion of Related Art
Generally, when integrated circuit semiconductor devices are fabricated, unit devices are separated by forming a shallow trench and a buried insulating layer in a silicon substrate. The shallow trench is used as an alignment key for alignment of the silicon substrate in subsequent processing. This alignment key is a kind of pattern, which is required to align an exposure mask at a precise position when a predetermined pattern is formed on the silicon substrate. The alignment key is formed at the same time as a pattern of a cell region and in a scribe line so as not to affect the cell region. Also, when integrated circuit semiconductor devices are fabricated, many material patterns are formed on the silicon substrate using photolithography and etch processes. Thus, when a first material pattern is formed on the silicon substrate and a second material pattern is formed on the first material pattern, to overlay the second material pattern exactly on the first material pattern, an overlay key is formed during the formation of the first material pattern. The overlay key is also formed in the scribe line so as not to affect the cell region.
FIGS. 1 through 4 are cross-sectional views illustrating a conventional method of fabricating an integrated circuit semiconductor device with an overlay key and an alignment key.
Referring to FIG. 1, a cell region, an overlay key region, and an alignment key region are defined in a silicon substrate 11. In the alignment key region, a shallow trench 13 is formed by a shallow trench isolation (STI) technique in the silicon substrate 11. The shallow trench 13 functions as the alignment key.
Thereafter, a thin insulating layer 15 is formed on the entire surface of the silicon substrate 11 with the cell region, the overlay key region, and the alignment key region. The insulating layer 15 is formed in the trench 13 in the alignment key region.
Next, a first photoresist pattern 17 is formed on the insulating layer 15 to cover the alignment key region. The portion of the first photoresist pattern 17 formed in the cell region is used to form an integrated circuit semiconductor device and the portion of the first photoresist pattern 17 formed in the overlay key region is used to form an overlay key.
Referring to FIG. 2, the insulating layer 15 is etched using the first photoresist pattern 17 as a mask, thereby forming an insulating pattern 15a. The portion of the insulating pattern 15a formed in the cell region is used for the integrated circuit semiconductor device. On the other hand, the portion of the insulating pattern 15a formed in the overlay key region functions as the overlay key for correcting alignment errors in a subsequent conductive pattern formation process.
Referring to FIG. 3, a conductive layer 19 is formed on the entire surface of the silicon substrate 11 where the insulating pattern 15a is formed on the cell region, the overlay key region, and the alignment key region. Thereafter, a second photoresist pattern 21 is formed on the conductive layer 19 using a photolithography process so as to cover the alignment key region.
Since the insulating pattern 15a used as the overlay key is too thin (i.e., a step difference between the silicon substrate 11 and the insulating pattern 15a is small), position data of the insulating pattern 15a cannot be obtained using an optical laser of an overlay measuring apparatus. Thus, it is impossible for an overlay measuring apparatus to measure an overlay state between the second photoresist pattern 21 and the insulating pattern 15a and to correct the alignment errors.
Thus, the overlay state between the second photoresist pattern 21 and the insulating pattern 15 is measured in an indirect manner, i.e., by using the overlay measuring apparatus to measure the location of the alignment key, such that the alignment errors of the second photoresist pattern 21 can be corrected.
Referring to FIG. 4, the second conductive layer 19 is etched using the second photoresist pattern 21 as a mask, thereby forming a conductive pattern 19a. As described above, the alignment errors of the second photoresist pattern 21 are corrected using the alignment key instead of the overlay key formed of the insulating pattern 15a. As a result, as illustrated by reference character “a” in the cell region, large alignment errors occur between the insulating pattern 15a and the conductive pattern 19a. 
As described above, in the conventional method of fabricating an integrated circuit semiconductor device with an overlay key and an alignment key, the thickness of the insulating pattern functioning as the overlay key is too small, and thus it is impossible to correct the alignment errors of the second photoresist pattern by using an overlay measuring apparatus. For this reason, the conventional method uses the alignment key in an indirect manner to correct the alignment errors of the second photoresist pattern. As a result, large alignment errors occur between the insulating pattern and the conductive pattern.